1. Field of the Invention
The present invention relates generally to precision optical measurement of the two process layers on a semiconductor wafer, and more particularly to a set of diffraction grating test patterns that are used in combination with rigorous diffraction grating analysis.
2. Description of Related Art
Lithography continues to be the key enabler and driver for the semiconductor industry. Metrology equipment and method for critical dimension (CD) and overlay control are the key elements of the lithography infrastructure. Overlay and CD control over large field sizes will continue to be a major concern for sub-100 nm lithography. Overlay requirements are among the most difficult technical challenges in lithography.
The main contributing factors to overlay error are the stage, the alignment system and the distortion signature. Errors can be broken down into stage motion or wafer alignment errors such as placement and rotation inaccuracies and field errors such as errors on the reticle and errors in camera magnification. These errors are correctable. Pincushion or barrel distortions, third-order field errors, are not correctable. The overlay errors must be routinely characterized for a given exposure tool. Three fundamental components of overlay are the alignment target detection capability, the stage positioning accuracy and precision, and the difference in lens distortion between two tools used to expose overlaying process layers.
Technologies used for overlay measurement include electrical test, scanning electron microscope (SEM), and optical microscope. Coherence probe microscopy (CPM), by adding an interferometer to the microscope, enables phase-based measurements that can pick up subtle differences in the index of refraction and the topography. Optical microscope technology has been the dominant measurement technique.
Overlay targets often are variations of box-in-a-box. The center of each box is calculated independently, and a difference between them is determined. Some metrology tools measure overlay error as a combination of linewidth measurements. To increase contrast, the boxes can be replaced with combinations of bars and frames, which add structure at the target's perimeter by providing two edges instead of one. A shortcoming is that there is no practical standard for overlay. Therefore, a true value for any particular overlay target is not known. Some fabs may periodically look at cross sections or make comparisons to electrical parameters, however, not only is this time consuming, it is relegated to the characterization environment, rather than being accomplished in production.
Alignment target detection became a show-stopper for many exposure tools with the proliferation of CMP levels, where very planarized metal layers present considerable challenges to finding and measuring a target's position.
One conventional solution uses a box-in-box test pattern. The details of this conventional solution is described in a section, for example, entitled “Semiconductor Pattern Overlay” in the Handbook of Critical Dimensions Metrology and Process Control, SPIE, vol. CR52, 1994, pp. 160-188.
The shortcomings of conventional solutions include, asymmetry of patterned line profile, aberrations in the illumination and imaging optics, and individual test pattern image sampling. One further shortcoming is that, for polished layers, the signal-to-noise (S/N) ratio in prior arts can be poor and affected by contrast variations in film thickness.
Accordingly, it is desirable to have a fast and flexible method and system for grating overlay patterns.